1. Technical Field
Embodiments of the present invention are directed to a memory module, such as a dual-inline memory module (DIMM). More particularly, embodiments of the present invention are directed to addressing an individual memory device, such as a dynamic random access memory (DRAM) device, on a memory module having a single precision resistor for calibration of the individual memory device.
2. Discussion of the Related Art
A Double-Data-Rate-II (DDR-II) synchronous dynamic random access memory (SDRAM) device is a high-speed complimentary metal oxide semiconductor (CMOS) random access memory (RAM) component. The DDR-II DRAM key features include: (1) posted column address strobe (CAS) with additive latency; (2) write latency=read latency xe2x88x921; (3) normal and weak strength data-output driver; (4) variable data-output impedance adjustment; and (5) an on-die termination (ODT) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at a cross point of the differential clocks. All inputs and outputs are synchronized with a single-ended data strobe signal or a differential data strobe signal pair in a source synchronous fashion.
The DDR-II synchronous DRAM (SDRAM) device supports driver calibration via off-chip driver (OCD) impedance adjustment. OCD impedance adjustment is performed using an extended mode register set (EMRS) mode. The extended mode register controls functions beyond those of the mode register set (which specifies the read latency and the working mode of the burst counter). These additional functions include, for example, temperature compensated self-refresh and partial self-refresh. The OCD protocol enables a memory controller to adjust the strength of the DRAM driver. The memory controller makes adjustments that cancel out variations seen during computer system operation due to changes in voltage and temperature. By making such adjustments, operation at higher frequencies are achieved because the driver variation range is reduced. Table I below illustrates a sample Off-Chip Driver instruction set utilizing address lines A9, A8, and A7 (bits 9, 8, and 7, respectively).
To adjust the output driver impedance, a controller issues the xe2x80x9cAdjustxe2x80x9d EMRS command along with a 4 bit burst code to the DDR-II SDRAM device as in Table I above. For this operation, burst length (BL) is set at 4 via a mode register set (MRS) command before activating the OCD protocol, and the controllers drive the burst code to all data signals at the same time. The driver output impedance is adjusted for all DDR-II SDRAM device data signals (DQs) simultaneously and after OCD calibration, all data signals (DQs) of a given DDR-II SDRAM device are adjusted to the same driver strength setting.
Present methods of calibrating a driver output impedance or other active circuit when enabled (Ron) yields large variations in the actual Ron values realized. Moreover, present methods of calibration of Ron require a precision resistor dedicated exclusively to each memory device (e.g., each SDRAM device) on the memory module (e.g., a DIMM), which makes the overall memory system costly.
Accordingly, what is needed is a method for addressing individual memory devices/components and for calibrating the output impedance of a memory device driver or other active circuit when enabled (Ron), that is more efficient, more cost effective, and does not require adding any additional signals or changing any protocols.